#ifndef __ARM5E__
  #include "LPC2100_addrs.h"
  // Helper macro to write to a memory mapped register
  #define REG(addr) (*(volatile unsigned long *)(addr))
#else
  #include "LPC3000_regs.h"
  #define HCLKPLL_LOCK    (1<<0)
  #define HCLKPLL_EN      (1<<16)
  #define DIV_HCLK_BY_1   (0x0)
  #define DIV_HCLK_BY_2   (0x1)
  #define DIV_PCLK_BY_15  (0xE<<2)
  #define DIV_PCLK_BY_4   (0x3<<2)
  /*
    HCLKPLL_200MHz
    Direct Mode
    Fclkin  =    13.0 MHz
    Fclkout = 199.333 MHz
    Fcco    = 199.333 MHz
    N = 3, M = 46 P = bypassed (PLL calculation value)
    N=2, M=45, P=0(Register bits)

    PD BC  DOC   FPC   P   N    M         S
    0  0   1     1     00  10   00101101  0
  */
  #define HCLKPLL_200MHz 0x645A
  /*
    HCLKPLL_60MHz
    Integer Mode
    Fclkin  =   13.0 MHz
    Fclkout =   58.5 MHz
    Fcco    =  234.0 MHz
    N = 2, M = 9 P = 4 (PLL calculation value)
    N=1, M=8, P=1(Register bits)

    PD BC  DOC   FPC   P   N    M         S
    0  0   0     1     01  01   00001000  0
  */
  #define HCLKPLL_60MHz 0x2A10
  #define NORMAL_RUN 0x4
#endif /* ifndef __ARM5E__ */

typedef struct _struct_test_t
{
  int a;
  char b;
  int * pInt;
} struct_test_t;


struct_test_t test =
{
  .a = 12,
  .b = 5,
  .pInt = (int*)0
};

void set_pll(void)
{
#ifdef __ARM5E__
  #ifdef PLL_60MHZ
    /* Set HCLK and PCLK dividers before turning on PLL */
    *HCLKDIV_CTRL = (DIV_HCLK_BY_1 | DIV_PCLK_BY_4);
    /* Set divider ratio */
    *HCLKPLL_CTRL = HCLKPLL_60MHz;
  #endif

  #ifdef PLL_200MHZ
    /* Set HCLK and PCLK dividers before turning on PLL */
    *HCLKDIV_CTRL = (DIV_HCLK_BY_2 | DIV_PCLK_BY_15);
    /* Set divider ratio */
    *HCLKPLL_CTRL = HCLKPLL_200MHz;
    /* Power up PLL*/
  #endif

  #if defined(PLL_60MHZ) || defined(PLL_200MHZ)
    /* Power up PLL*/
    *HCLKPLL_CTRL = ((*HCLKPLL_CTRL) | (HCLKPLL_EN));
    /* Wait for PLL to Lock */
    while( ((*HCLKPLL_CTRL) & (HCLKPLL_LOCK)) == 0)
    {};
    /* Enter Normal Run mode */
    *PWR_CTRL = (*PWR_CTRL)|(NORMAL_RUN);
  #endif
#else
  // Set the memory accelarator settings for optimum flash access
  REG(SYSCON_MAMCR) = 0x0;
  REG(SYSCON_MAMTIM) = 0x3;
  REG(SYSCON_MAMCR) = 0x2;

  // set the pll multiplier M to be 4, the value set in register is (M-1);
  // set the pll divider P to be 2 so that Fcco is in the range of 156 MHz to 320 MHz.
  REG(SYSCON_PLLCFG) = 0x23;
  // configure pll to be active
  REG(SYSCON_PLLCON) = 0x1;
  // make the changes effective by setting the pll feed sequence
  REG(SYSCON_PLLFEED) = 0xAA;
  REG(SYSCON_PLLFEED) = 0x55;

  // Wait until pll is locked to specified frequency and relevant status is set
  while ((REG(SYSCON_PLLSTAT) & 0x400) == 0);

  // configure pll to be active and used as system clock source
  REG(SYSCON_PLLCON) = 0x3;
  // make the changes effective by setting the pll feed sequence
  REG(SYSCON_PLLFEED) = 0xAA;
  REG(SYSCON_PLLFEED) = 0x55;

  // check if pll is enabled,locked and connected
  while ((REG(SYSCON_PLLSTAT) & 0x700) != 0x700);

#endif
}
