   PRESERVE8 ;Added to avoid Error: L6238E: startup.o(Vect) contains invalid call from '~PRES8' function to 'REQ8'
   AREA    Vect, CODE, READONLY
   CODE32
   ENTRY
   IMPORT __main
   IMPORT set_pll
   EXPORT __user_initial_stackheap
               
;/******************************************************************************
;*          Exception vector table - common to all ARM-based systems           *
;******************************************************************************* 
;* Common to all ARM-based systems. See ARM Architecture Reference Manual,     *
;* Programmer's Model section for details. Table entries just jump to handlers *
;* (using full 32-bit addressing).                                             *
;******************************************************************************/
_int_vectors

        ldr     pc, do_reset_addr     
        ldr     pc, do_undefined_instruction_addr
        ldr     pc, do_software_interrupt_addr
        ldr     pc, do_prefetch_abort_addr
        ldr     pc, do_data_abort_addr
        DCD 	 0x0 ;/* ARM-reserved vector */
        ldr     pc, do_irq_addr ;
        ldr     pc, do_fiq_addr

do_reset_addr                  DCD   do_reset
do_undefined_instruction_addr  DCD   do_undefined_instruction
do_software_interrupt_addr     DCD   do_software_interrupt
do_prefetch_abort_addr         DCD   do_prefetch_abort
do_data_abort_addr             DCD   do_data_abort
do_irq_addr                    DCD   do_irq
do_fiq_addr                    DCD   do_fiq

;/******************************************************************************
;*                         Yet to be implemented exceptions                    *
;*******************************************************************************
;* Just fall through to reset exception handler for now                        *
;******************************************************************************/                                                                            
do_undefined_instruction
do_software_interrupt
do_prefetch_abort
   ;
   MRC p15, 0, r0, c5, c0, 0 ;read IFSR
   MRC p15, 0, r1, c5, c0, 1 ;read IFSR
do_data_abort
   MRC p15, 0, r0, c6, c0, 0
do_irq
do_fiq

;/******************************************************************************
;*                            System reset handler                             *
;******************************************************************************/
do_reset

 if :DEF:ARM7
   if :DEF:FLASH
ram_end EQU 0x40004000
   endif
   if :DEF:RAM
ram_end EQU 0x40010000
   endif
 else
ram_end EQU 0x08010000
 endif
  
   LDR r2, =ram_end ;Get top of RAM
   MRS r0, CPSR ;Save current processor mode

   ; Initialize the Undef mode stack
   BIC r1, r0, #0x1f
   ORR r1, r1, #0x1b
   MSR CPSR_c, r1
   ;Keep top 32 bytes
   SUB sp,r2,#0x20

   ; Initialize the Abort mode stack
   BIC r1, r0, #0x1f
   ORR r1, r1, #0x17
   MSR CPSR_c, r1
   SUB sp,r2,#0x500

   ; Initialize the IRQ mode stack
   BIC r1, r0, #0x1f
   ORR r1, r1, #0x12
   MSR CPSR_c, r1
   SUB sp,r2,#0x800

   ; Return to the original mode.
   MSR CPSR_c, r0
   ; Initialize the stack for user application
   SUB sp,r2,#0xb00                 
   msr     cpsr_c, #0x13	  ;  /* I=0 F=0 T=0 MODE=supervisor */


 if :DEF:ARM7
 else                                          
    ;Remap vectors in IRAM
   
   LDR r2,=0x40004014
   MOV r1,#0x1
   STR r1,[r2]
      if :DEF:VFP9
         ;VFP9 Initialization
         ;Set EN[30] within the Exception Status Word FPEXC.        
         mov r0,#0x40000000
         MCR     p10, 7, r0, c8, c0, 0
      endif
;/* Enable ARM9 Caches */

      if :DEF:ICACHE
         MRC     p15, 0, r0, c1, c0, 0       ; read CP15 register 1 into r0
         ORR     r0, r0, #(0x1  <<12)        ; enable I Cache
         MCR     p15, 0, r0, c1, c0, 0       ; write CP15 register 1
      endif
      
      if :DEF:DCACHE      
         ; Enables the D-Cache and the MMU
    ;  location of the translation table in memory
    ldr    r0,=0x0800C000
    ; Set section 0 in translation table
    ldr    r1,=0x0000C1E
    str    r1,[r0,#0x0]
    ; Set section 512 in translation table
    ldr    r1,=0x8000C1E
    str    r1,[r0,#0x200]
    MCR    p15, 0, r0, c2, c0, 0         ; Translation table base register
    ; Mark Peripheral register area as not cacheable
    ldr    r1,=0x40000C12
    mov    r3,#0x1000
    str    r1,[r0,r3]
    MOV    r1,#-1
    MCR    p15, 0, r1, c3, c0, 0         ; Domain Access Control register All domains to Manager
    LDR    r2,=0x0000007d
    MRC    p15, 0, r0, c1, c0, 0       ; read CP15 register 1 into r0
    ORR    r2,r0,r2
    MCR    p15, 0, r2, c1, c0, 0         ; Control register -> Async, MMU on, DCache on
      endif
 
 endif
 
   mov     r0, #0     ;         /*  no arguments  */
   mov     r1, #0     ;         /*  no argv either */
        
   ;   /* Enable interrupts, enter supervisor mode and branch to start of 'C' code */
   bl set_pll
   b      __main

;Allocate heap

__user_initial_stackheap    
    SUB   r1,r1,#0x800
    MOV   pc,lr

   END
   