/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : QTMR0.C
**     Project   : bldc_hall_demo
**     Processor : MC56F8006_48_LQFP
**     Beantype  : Init_TMR
**     Version   : Bean 01.131, Driver 02.01, CPU db: 3.00.177
**     Compiler  : Metrowerks DSP C Compiler
**     Date/Time : 28.11.2008, 14:28
**     Abstract  :
**         This "Init_TMR" Peripheral Inspector implements the
**         Quad Timer module (TMR), basic initialization
**         and settings.
**     Settings  :
**         Timer counter device        : TMR0
**
**         Operation mode              : Count mode
**         Count once                  : count repeatedly
**         Count length                : roll-over
**         Count direction             : up
**         Master mode                 : Disabled
**         External OFLAG force        : Disabled
**         Forced OFLAG value          : 0
**         Force OFLAG ouput           : no
**         Output enable               : no
**         Output polarity             : true
**         Input  polarity             : true
**         Co-channel init.            : Disabled
**
**         Primary source              : prescaler (IP BUS clock / 128)
**         Secondary source            : counter 0 input pin
**
**         Input capture mode          : Enabled
**             Load capture register   : on any edge of input
**
**         Output mode                 : asserted while counter is active
**
**         Compare load control 1      : Disabled
**         Compare load control 2      : Disabled
**
**         Debug mode action           : Normal operation
**
**         Fault                       : Disabled
**
**         Alternative load            : Disabled
**
**         Interrupts
**             Timer compare           : Disabled
**             Timer overflow          : Disabled
**             Input edge              : Enabled
**             Timer compare 1         : Disabled
**             Timer compare 2         : Disabled
**             ISR name                : ISR_TimerCapture
**             Interrupt name          : INT_TMR0
**             Priority                : 2 (USER4)
**     Contents  :
**         Init - void QTMR0_Init(void);
**
**     (c) Copyright UNIS, a.s. 1997-2008
**     UNIS, a.s.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : info@processorexpert.com
** ###################################################################*/

/* MODULE QTMR0. */

#include "QTMR0.h"

/*
** ###################################################################
**
**  The following method must be implemented by the user in one
**  of the following modules:
**
**    #pragma interrupt
**    void ISR_TimerCapture(void)
**
**  Modules:
**       bldc_hall_demo
**       Events
**
** ###################################################################
*/

/*
** ===================================================================
**     Method      :  QTMR0_Init (bean Init_TMR)
**
**     Description :
**         This method initializes registers of the TMR module
**         according to this Peripheral Initialization Bean settings.
**         Call this method in the user code to initialize the
**         module. By default, the method is called by PE
**         automatically; see "Call Init method" property of the
**         bean for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void QTMR0_Init(void)
{
  setReg16(TMR0_COMP1, 0x00);          /* Set the Compare register 1 */ 
  setReg16(TMR0_COMP2, 0x00);          /* Set the Compare register 2 */ 
  setReg16(TMR0_CAPT, 0x00);           /* Set the Capture register */ 
  setReg16(TMR0_LOAD, 0x00);           /* Set the Load register */ 
  setReg16(TMR0_CNTR, 0x00);           /* Set the Counter register */ 
  /* TMR0_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=1,IPS=0,INPUT=0,CAPTURE_MODE=3,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
  setReg16(TMR0_SCTRL, 0x04C0);        /* Set the Status and control register */ 
  /* TMR0_CMPLD1: COMPARATOR_LOAD_1=0 */
  setReg16(TMR0_CMPLD1, 0x00);         /* Set the Comparator load register 1 */ 
  /* TMR0_CMPLD2: COMPARATOR_LOAD_2=0 */
  setReg16(TMR0_CMPLD2, 0x00);         /* Set the Comparator load register 2 */ 
  /* TMR0_CSCTRL: DBG_EN=0,FAULT=0,ALT_LOAD=0,??=0,??=0,??=0,??=0,TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
  setReg16(TMR0_CSCTRL, 0x00);         /* Set the Comparator status/control register */ 
  /* TMR0_FILT: ??=0,??=0,??=0,??=0,??=0,FILT_CNT=0,FILT_PER=0 */
  setReg16(TMR0_FILT, 0x00);           /* Set Filter register */ 
  /* TMR0_CTRL: CM=1,PCS=0x0F,SCS=0,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */
  setReg16(TMR0_CTRL, 0x3E00);         /* Set the Control register */ 
}

/* END QTMR0. */

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.99 [04.17]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
